Semiconductor manufacturing processes balance various parameters to produce the complex integrated circuit devices common today. This balance may result in some nominal process variations that create deviations in integrated circuit device performance. These deviations often require adjusting the manufacturing process to re-center certain digital logic parameters.
These adjustments often impact second order devices, such as resistors. This impact may be diminished by applying a re-centering scheme to these second order devices. The modifications to the second order devices resulting from the re-centering, however, typically impart additional changes to the digital logic parameters. Thus, these solutions require a continuing trade-off between process optimization directed to the digital logic and optimization directed to the second order devices.
This trade-off has spawned the development of a variety of mitigation methods presently used in designing semiconductor technology or products. These methods include redesigning products to run a on particular manufacturing line, modifying second order devices to adjust second order properties, and using additional masks in the manufacturing process to tune second order devices separately from the digital logic. These techniques require relatively large investments of time and money that ultimately increase the cost of the final product.